The present technique relates to an apparatus and method for handling access requests.
Processing circuitry can be arranged to perform data processing operations on data, where the operations identify the data using virtual addresses, and the virtual addresses are mapped to physical addresses within a memory system. Within such a system, a cache may arranged as a virtually indexed physically tagged (VIPT) cache, where a cache index is derived at least partially from a specified virtual address in order to identify at least one cache entry within the cache (for example to identify a set within a set associative cache), and then the detection of whether a hit is present is determined by comparing a physical address portion stored in the relevant cache entry with a tag portion of the physical address that corresponds to the specified virtual address. Within such a cache, an aliasing condition can arise when multiple virtual addresses map to the same physical address, and the cache can be configured so as to prevent multiple cache entries simultaneously storing data for the same physical address.
Whilst such an approach can effectively deal with the aliasing condition, when the processing circuitry is executing multiple program threads and one or more of the program threads can perform exclusive operations, this can give rise to live-lock issues arising. In particular, for an exclusive operation to complete, it may be required that the data being processed by that exclusive operation remains within the cache throughout performance of the exclusive operation, but the steps taken by the cache to prevent multiple cache entries simultaneously storing data for the same physical address can cause the data to be evicted when different threads are seeking to access the same data, thus preventing the exclusive operation from completing.
It would be desirable to provide an effective mechanism for avoiding such a live-lock scenario arising.